The technology disclosed in the specification relates to a semiconductor device and a manufacturing method thereof. More particularly, the technology disclosed in the specification relates to a semiconductor device having a complementary field effect transistor formed by an n-channel field effect transistor and a p-channel field effect transistor.
With recent improvement of information communication equipments, demand for the processing capability of semiconductor devices such as LSI (Large Scale Integration) has been increasingly strict, and the operation speed of transistors has been increased in response to the demand. Especially a complementary field effect transistor formed by an n-channel field effect transistor and a p-type field effect transistor has been widely used because of its low power consumption. The operation speed of the complementary field effect transistor has been increased mainly by reducing the dimensions of the transistor structure, and such increase in operation speed has been supported by the progress in lithography technology for processing semiconductor elements.
In recent years, however, required minimum processing dimensions (minimum processing dimensions of the gate) have become smaller than the light wavelength level used in lithography, and further reduction in dimensions of the transistor structure is therefore difficult. It has been proposed to increase the transistor operation speed by increasing the mobility by distorting silicon of the channel portion. This method is based on the fact that the mobility (effective mass) of electrons changes when a silicon crystal is distorted.
For example, DSL (Dual Stress Liner) using contact liners and SMT (Stress Memorization Technology) have been introduced in D. V. Singh, et al., (20.5), IEDM 2005 as a stress application method for distorting silicon. In the SMT, high-temperature heat treatment is performed while applying a stress to a substrate, so that the stress remains on the substrate.
A complementary field effect transistor using DSL is studied in C. D. Sheraw et al., (2-1) VSLI 2005. C. D. Sheraw et al., (2-1) VSLI 2005 shows the crystal orientation, the stress direction to the channel, and change in characteristics of n-channel and p-channel transistors, and cross-sectional shapes of the transistors.
Regarding an n-channel transistor which has a silicon substrate having a (100) main surface and has a <110> channel direction, the mobility is improved by applying a tensile stress to the channel in the gate length direction and the gate width direction and applying a compressive stress to the channel in a direction perpendicular to the substrate surface. The mobility of a p-channel transistor having a <110> channel direction is improved by applying a compressive stress to the channel in the gate length direction and applying a tensile stress to the channel in the gate width direction.
Regarding an n-channel transistor which has a silicon substrate having a (100) main surface and has a <100> channel direction, the mobility is significantly improved by applying a tensile stress to the channel in the gate length direction, and the mobility is improved by applying a compressive stress to the channel in the gate width direction and in a direction perpendicular to the substrate surface. The mobility of a p-channel transistor having a <100> channel direction is somewhat improved by compressing the channel in the gate length direction. Note that the mobility of a complementary field effect transistor can be improved by applying a stress of the same direction to an n-channel transistor and a p-channel transistor when the complementary field effect transistor has a <110> channel direction.
Regarding a manufacturing method of a semiconductor device, it has been studied to independently form the respective channel directions of an n-channel transistor and a p-channel transistor of a complementary field effect transistor by using a lamination technology. In this case, it is effective to use an n-channel transistor having a <100> channel direction and a p-channel transistor having a <110> channel direction.
FIG. 9 shows a process flow of a conventional DSL technology. This process flow shows the steps from element isolation formation to contact liner formation.
In the conventional DSL technology of FIG. 9, element isolation is first formed by STI (Shallow Trench Isolation), and ion implantation for well formation is then performed in an n-channel transistor formation region (hereinafter, referred to as “N-channel region”) and a p-channel transistor formation region (hereinafter, referred to as “P-channel region”).
Next, threshold voltage (Vt) implantation is performed in each transistor formation region in order to determine a transistor threshold value. A gate insulating film is then formed over a substrate, and polysilicon as a gate electrode material is deposited over the gate insulating film. A dopant is then implanted to the gate electrode material on the N-channel region and the P-channel region, and a resist gate pattern is formed by lithography. By using the resist gate pattern as a mask, the polysilicon is etched to form polysilicon gate electrodes.
Extension implantation is then performed in each transistor formation region to form an extension region on both sides of the gate electrode. A layered film of an oxide film and a nitride film is then deposited over the whole substrate surface, and etch-back is performed to form a sidewall. N-type impurity ions and P-type impurity ions are then implanted to the N-channel region and the P-channel region, respectively. Heat treatment is performed to activate the dopants, whereby source/drain regions are formed. Silicide of nickel, that is, silicide of a high melting point metal, is then formed by a known method over the gate electrodes and the active regions.
After the sidewall is removed by etching, a plasma nitride film is deposited over the whole substrate surface. Heat treatment is then performed to cause film shrinkage, whereby a contact liner of the N-channel region is formed. An oxide film is then deposited over the whole substrate surface as a film serving both as an etching stopper film and a resist interface layer. A resist mask having an opening in the P-channel region is then formed by lithography. The plasma nitride film on the P-channel region is removed by etching by using the resist mask. The resist mask is then removed and a plasma nitride film is deposited over the whole substrate surface as a contact liner of the P-channel region. An oxide film is then deposited over the whole substrate surface as a resist interface layer. A resist mask having an opening in the N-channel region is then formed by lithography. The plasma nitride film on the N-channel region is removed by etching by using the underlying oxide film as an etching stopper. The resist mask is then removed and a contact formation interlayer film is formed by a known method. Contact holes are then formed.
FIG. 10A is a cross-sectional view in the gate length direction of a semiconductor device formed by the above process.
As shown in FIG. 10A, an n-channel gate 1203 and a p-channel gate 1204 are respectively formed in an N-channel region 1201 and a P-channel region 1202 in the conventional semiconductor device. A sidewall underlying film 1205 is formed on the respective sidewalls of the n-channel gate 1203 and the p-channel gate 1204. An element isolation region 1206 isolates the N-channel region 1201 and the P-channel region 1202 of the substrate from each other.
Source/drain regions 1207 containing N-type impurities are formed in an upper part of the substrate in the N-channel region 1201, and source/drain regions 1207 containing P-type impurities are formed in an upper part of the substrate in the P-channel region 1202. A silicide layer 1209 is formed on the source/drain regions 1207. A silicide layer 1208 is formed on the n-channel gate 1203 and the p-channel gate 1204.
A contact liner 1210 is formed over the substrate, the sidewall underlying film 1205, and the silicide layer 1208 in the N-channel region 1201. A contact liner 1212 is formed over the substrate, the sidewall underlying film 1205, and the silicide layer 1208 in the P-channel region 1202. An interlayer insulating film 1219 is formed over each contact liner. Contacts 1221 are also formed so as to extend through the interlayer insulating film 1219 to the respective silicide layers 1209. A resist interface layer 1211 is formed between the contact liner 1210 of the N-channel region 1201 and the interlayer insulating film 1219. A resist interface layer 1213 is formed between the contact liner 1212 of the P-channel region 1202 and the interlayer insulating film 1219.
In the conventional semiconductor device, a tensile stress can be applied in the gate length direction to the channel of a MOS (Metal Oxide Semiconductor) transistor formed in the N-channel region 1201 by the contact liner 1210 formed by film shrinkage. The mobility of the N-channel MOS transistor can thus be improved. The mobility of a P-channel MOS transistor, on the other hand, can be improved by applying a compressive stress to the channel of the P-channel MOS transistor.
By using the transistors which are subjected to a stress by the contact liner, transistor characteristics can be improved and the transistor gate width (the width in the direction parallel to the substrate surface and perpendicular to the channel direction) can be reduced, thereby enabling reduction in chip size. Moreover, since the transistor characteristics are improved, the transistor operation speed can be increased.